Preliminaries

1. All tests are peformed using the UCSC MUX and the LBNL ROM. The clock frequency was 40 MHZ, the duty cycle was 50%. Most of the data shown here were taken with benchtop power supplies, and with the HDI and the detectors mounted in the UCSB ringframe. The UCSB HDI Tail Adaptor was used to connect the HDIs to the the Matching Card. Data were also taken with the detector mounted in the commissioning box, using CAEN supplies, and tail from ELIFlex.

2. Methods to extract noise, gains, and intercepts are documented here. The threshold scans were performed firing 16 channels at a time. We used chip parameters communicated to us by Amedeo Perazzo.

3. The HDIs are loaded with rad hard V2 chips in configuration A with high gain selected.

4. The two HDIs are H1-13 and H1-29.

5. H1-13 is a backward HDI, connected to DFA D02B-8, H1-29 is a forward HDI connected to DFA D02F-4

6. The chip numbering convention throughout this document is the following:

   • Chips 0-6 are on the n-side. Chip 0 has address 0, chip 6 has address 6.

   • Chips 7-13 are on the p-side. Chip 7 has address 0, chip 13 has address 6.

   • The serial numbers of the chips, according to the information from Aurel are: