SVT Test Beam Thresholds

The thresholds at the August 97 test beam were set using the following procedure:

The channel by channels offsets and gains were first measured, for a given shaping time, using the procedure documented here
For each chip, the mean offset was recorded, in units of DAC counts
Nominal thresholds in fC were then set using the mean offset for a given chip, and assuming the following parameters:
- Threshold DAC : 4.29 mV/count
- Typical gain at 100 nsec shaping time : 65 mV/fC
- Typical gain at 200 nsec shaping time : 83 mV/fC
- Typical gain at 400 nsec shaping time : 92 mV/fC

The actual chip-by-chip thresholds used at the testbeam are given in the following four tables.

**Thresholds set on the chips for the Layer 2 module for a shaping time of 100 nsec**
chip	side	thresh 0.6 fC	thresh 0.7 fC	thresh 0.8 fC	thresh 0.9 fC	thresh 1.0 fC	thresh 1.2 fC	thresh 1.4 fC
0	n	51	49	48	46	45	42	39
1	n	55	53	52	50	49	46	43
2	n	57	55	54	52	51	48	45
3	n	52	50	49	47	46	43	40
4	n	52	50	49	47	46	43	40
5	n	51	49	48	46	45	42	39
6	n	dead	dead	dead	dead	dead	dead	dead
0	p	48	46	45	43	42	39	36
1	p	44	42	41	39	38	35	32
2	p	47	45	44	42	41	38	35
3	p	49	47	46	44	43	40	37
4	p	50	48	47	45	44	41	38
5	p	49	47	46	44	43	40	37
6	p	51	49	48	46	45	42	39

**Thresholds set on the chips for the Layer 5 module for a shaping time of 100 nsec**
chip	side	thresh 0.6 fC	thresh 0.7 fC	thresh 0.8 fC	thresh 0.9 fC	thresh 1.0 fC	thresh 1.2 fC	thresh 1.4 fC
0	n	58	56	55	53	52	49	46
1	n	58	56	55	53	52	49	46
2	n	58	56	55	53	52	49	46
3	n	dead	dead	dead	dead	dead	dead	dead
0	p	54	52	51	49	48	45	42
1	p	53	51	50	48	47	44	41
2	p	53	51	50	48	47	44	41
3	p	55	53	52	50	49	46	43

**Thresholds set on the chips for the Layer 2 module for a shaping time of 200 nsec**
chip	side	thresh 0.6 fC	thresh 0.7 fC	thresh 0.8 fC	thresh 0.9 fC	thresh 1.0 fC	thresh 1.2 fC	thresh 1.4 fC
0	n	47	45	43	41	39	35	31
1	n	52	50	48	46	44	30	36
2	n	55	53	51	49	47	43	39
3	n	47	45	43	41	39	35	31
4	n	48	46	44	42	40	36	32
5	n	47	45	43	41	39	35	31
6	n	dead	dead	dead	dead	dead	dead	dead
0	p	43	41	39	37	35	31	27
1	p	37	35	33	31	29	25	21
2	p	42	40	38	36	34	30	26
3	p	44	42	40	38	36	32	28
4	p	45	43	41	39	37	33	29
5	p	44	42	40	38	36	32	28
6	p	47	45	43	41	39	35	31

**Thresholds set on the chips for the Layer 5 module for shaping times of 200 nsec (pside) and 400 nsec (nside)**
chip	side	thresh 0.6 fC	thresh 0.7 fC	thresh 0.8 fC	thresh 0.9 fC	thresh 1.0 fC	thresh 1.2 fC	thresh 1.4 fC
0	n	52	50	47	45	43	38	34
1	n	52	50	47	45	43	38	34
2	n	53	51	48	46	44	39	35
3	n	dead	dead	dead	dead	dead	dead	dead
0	p	51	49	47	45	43	39	35
1	p	51	49	47	45	43	39	35
2	p	50	48	46	44	42	38	34
3	p	55	53	51	49	47	43	39

Claudio Campagnari

Page Last Updated: Sep 30, 1997